Junction-side illuminated silicon detector arrays

ABSTRACT

A junction-side illuminated detector array of pixelated detectors is constructed on a silicon wafer. A junction contact on the front-side may cover the whole detector array, and may be used as an entrance window for light, x-ray, gamma ray and/or other particles. The back-side has an array of individual ohmic contact pixels. Each of the ohmic contact pixels on the back-side may be surrounded by a grid or a ring of junction separation implants. Effective pixel size may be changed by separately biasing different sections of the grid. A scintillator may be coupled directly to the entrance window while readout electronics may be coupled directly to the ohmic contact pixels. The detector array may be used as a radiation hardened detector for high-energy physics research or as avalanche imaging arrays.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0001] This invention was made with government support under SmallBusiness Innovation Research program (Grant # DE-FG03-99ER82854) awardedby the Department of Energy. The Government has certain rights in thisinvention.

FIELD OF THE INVENTION

[0002] The present invention relates to radiation detectors and morespecifically, to a structure of and a method for fabricating pixelatedsilicon detector arrays and photodetector arrays.

BACKGROUND OF THE INVENTION

[0003] Many applications can benefit from a development of advancedpixelated silicon detector arrays with superior characteristics for darkleakage current, quantum efficiency, and production yields. One suchapplication involves silicon photodetector arrays that can be used toconstruct gamma-ray cameras with very high resolution.

[0004] Highly pixelated silicon photodetector arrays coupled to closelymatched parallel piped CsI(Tl) scintillator arrays are a known basis forsolid state gamma-ray cameras capable of imaging a wide variety ofsubjects ranging from small animals in the laboratory to whole humanbodies. One example of silicon photodetector arrays for radiationimaging is disclosed in U.S. Pat. No. 5,773,829 entitled “RadiationImaging Detector,” issued Jun. 30, 1998 to Iwanczyk and Patt, which ishereby incorporated by reference in full.

[0005] Large-sized solid state gamma-ray cameras employing suchradiation imaging detectors typically require low cost and high-yieldsemiconductor photodetector array structures with superior performanceand competitive prices compared to those of the existing clinicalsystems for Single Photon Emission Computed Tomography (SPECT) whichutilize known vacuum Photomultiplier Tube (PMT) technologies.

[0006] Other broad applications including radiation hardened detectorarrays for high-energy physics research, and new designs of avalancheimaging arrays (photodetectors with an internal gain) would also benefitfrom a development of low cost, high-yield detector array structures.

[0007] Typical silicon photodiode arrays with parallel signal readoutare based on (p+)−(n)−(n+) structures constructed on high resistivity(0.1-10 k ohm-cm) silicon wafers. P+ contacts forming junctions in then-type substrate are constructed in the form of a diode array. A commonn+ contact forms an ohmic contact, and is used as an entrance window(light sensitive window).

[0008] Structures wherein the n+ (ohmic) contact is used as the entrancewindow for light, x-rays, gamma rays, or particles, and in which the p+(junction) contacts are used as the readout are referred to as back-sideilluminated photodiodes or back-illuminated photodiodes, thejunction-side commonly being referred to as the front-side. Suchback-side illuminated diode arrays are known, and are described in apaper entitled “Development of Low Noise, Back-Side Illuminated SiliconPhotodiode Arrays,” by S. E. Holland, N. W. Wang, and W. W. Mosespublished in IEEE Transactions on Nuclear Science Vol. 44 No. 3 1997.

[0009] In the back-side illuminated photodiodes, the (p+−(n) junctionarray, which is created on the non-light sensitive side of the chip, isgenerally used only for signal readout and therefore can usually bebonded directly to the readout chip or circuitry without obstructing thelight from a scintillator. The opposite side (ohmic side) is typicallycoupled to the scintillator for light detection. This type of arraytypically operates only in fully depleted mode, which usually requiresreverse bias of more than 70 V for the standard 5000 ohm-cm resistivitysilicon or higher biases for lower resistivity material.

[0010] In order to achieve stable I-V characteristic and a low reversecurrent value, each of the p+ pixels typically incorporates a fieldplate and surrounding guard rings to optimize the potential distributionaround the pixel and to drain out the surface leakage current. Thesestructures typically suffer from the following shortcomings:

[0011] 1. The requirement of high light sensitivity at the ohmic contactconflicts with the technological requirements for effective gettering ofthe bulk material necessary for maintaining long life times of minoritycarriers. For effective gettering of the detector bulk, highconcentrations of phosphorus dopant and a relatively large thickness ofdoped material is required in the n+ contact. On the other hand, inorder to ensure high light sensitivity, the contact has to be made asthin as possible with an optimized doping profile. Thinning of thecontact is at the cost of the gettering process, and it usually causesan increase in the dark leakage current in the constructed arrays;

[0012] 2. In the known back-side illuminated structures, in order toachieve full depletion at low bias voltages and to reduce the bulkgeneration current component, designers favor the use of very thinwafers. However, this creates technological problems due to the lack ofmechanical strength of the thin silicon material;

[0013] 3. Reduction of the surface leakage current is usually achievedby constructing a field plate structure at the periphery of individualpixels. However, this is known to lead to generation of defects at theinterface between SiO₂ and Si in the field plate. These defectstypically are a source of excess reverse current. Some reduction of thedefect density can usually be achieved by use of costly high purityprocesses and materials;

[0014] 4. For low leakage operation, the back-side illuminatedstructures generally require guard ring structures typically surroundingeach individual pixel, and at least surrounding small groups (32 to 64)of pixels. These guard ring structures require additional physical spacebetween the pixels and create problems in building high-density arraysor mosaics of such arrays.

SUMMARY OF THE INVENTION

[0015] In one embodiment according to the present invention, detectorarray is formed on a semiconductor material having a first side and asecond side. The detector array includes an entrance window formed onthe first side. The entrance window is used to receive radiation. Thedetector array also includes an array of detectors formed on the secondside. One or more of the detectors are used for detecting the radiationreceived via the entrance window. The entrance window forms a junctionwith the semiconductor material, and the detectors include pixelatedohmic contacts.

[0016] In another embodiment according to the present invention, amethod of forming a detector array on a semiconductor material having afirst side and a second side is provided. An entrance window is formedon the first side. The entrance window is used for receiving radiation.An array of detectors is formed on the second side. One or more of thedetectors are used for detecting the radiation received via the entrancewindow. The entrance window forms a junction with the semiconductormaterial, and the detectors include pixelated ohmic contacts.

[0017] In yet another embodiment of the present invention, a compositedetector array includes multiple detector arrays.

[0018] In still another embodiment of the present invention, a detectorarray is formed on a semiconductor material having a first side and asecond side. The detector array includes entrance window means formed onthe first side. The entrance window means is used for receivingradiation. The detector array also includes an array of detector meansformed on the second side. One or more of the detector means are usedfor detecting the radiation received via the entrance window means. Theentrance window means form a junction with the semiconductor material,and the detector means include pixelated ohmic contacts.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other features of the present invention may be morefully understood from the following detailed description, taken togetherwith the accompanying drawings, wherein similar reference charactersrefer to similar elements throughout and in which:

[0020]FIG. 1 is a cross-sectional view of a detector array produced fromhigh resistivity n-type Si (top) and back-side view (bottom) in anembodiment according to the present invention;

[0021]FIG. 2 is a cross-sectional view of a detector array produced fromhigh resistivity p-type Si (top) and back-side view (bottom) in anembodiment according to the present invention;

[0022]FIG. 3 is a cross-sectional view of an avalanche detectorconstructed from high resistivity n-type Si in an embodiment accordingto the present invention;

[0023]FIG. 4 is a top view of the topology of a detector array showingseparate grids for changing of the pixel sizes by biasing appropriategrids in an embodiment according to the present invention;

[0024]FIG. 5 is a top view illustrating the method for joint biasing ofindividual grid arrangements by coupling grids together; and

[0025]FIG. 6 is a top view illustrating the method for individuallybiasing the grid arrangements.

DETAILED DESCRIPTION

[0026] In one embodiment of the present invention, a new junction-sideilluminated silicon detector array of pixelated silicon detectors and amethod of constructing the same are disclosed. The detectors may beconstructed from high resistivity silicon (Si) with a common junctioncontact on the front-side and ohmic contacts implemented as a pixelatedarray on the back-side.

[0027] In the present invention, the junction contact preferably coversthe entire detector array and serves as a front-side light, x-ray, gammaray and/or particle sensitive window without dead areas. To isolate theindividual ohmic contact pixels on the back-side, the inter-pixel gapspreferably contain junction separation implants that surround each pixelin the form of a grid or rings created on the entire array. In this way,the light entrance contact of the present invention may be improved interms of depth and profile for better light sensitivity.

[0028] The entrance window of the present invention preferably allowsfor better gettering of the bulk material than in the back-sideilluminated method, thus allowing for reduction of bulk generatedcurrent. In addition, the operational bias of the present invention maybe up to four times lower than required for the traditional back-sideilluminated structures. Using the structure in an embodiment accordingto the present invention, the field plates may be eliminated, resultingin decrease of the excess current, and the guard-ring structures may beeliminated, reducing the gap between pixels, and thus allowing forconstruction of high-density arrays.

[0029] The photodetector array construction of the present invention mayhave significant advantages in the mass production process due to loweroperating bias voltages, significantly simplified testing, use ofthicker Si wafers (less breakage during processing), and possible veryhigh production yields. Use of thicker wafers opens up additionalpossibilities of processing 6″ (instead of 4″) or even larger diameterwafers leading to the possibility of further reduction in productioncosts.

[0030] The photodetector arrays of the present invention may have one ormore of the following advantages over the conventional devices:

[0031] 1) The light entrance contact may be formed by boron implantationor other doping methods such as diffusion of deposited dopants and maybe improved in terms of depth and profile for better light sensitivity;

[0032] 2) The technology of photosensitive contacts does not interferesubstantially with the requirements of the improved gettering of thebulk material that allows reduction of the bulk generated current;

[0033] 3) The operational bias may be up to four times lower thanrequired for the traditional back-side illuminated structures;

[0034] 4) The field plates, the guard ring structures, and associatedexcess current may be eliminated;

[0035] 5) Construction of pixels without using guard rings may allowreducing the gap between pixels and may make the high-density arraysfeasible;

[0036] 6) Testing of the proposed structures may be significantlysimplified compared to the traditional designs; and

[0037] 7) The lower bias voltages combined with simpler and moreoptimized technology may lead to the significant improvement inproduction yields.

[0038] The detector array of the present invention may also be used as aradiation hardened detector for high-energy physics research fordetection of particles, x-ray, or gamma rays. The radiation hardness ofthis structure may be achieved through simplified construction (lack ofthe field plates and excessive guard rings) and relatively low operatingbias voltages. The present invention may also find other broadapplications including, but not limited to, applications as noveldesigns for avalanche imaging arrays (photodetectors with an internalgain).

[0039] The signals may be coupled from the pixelated ohmic contacts inthe present invention to the readout electronics. Because the readout isdone on the opposite side of the entrance window on the silicon wafer,it is possible to couple the device to a scintillator, a scintillatorarray, a light guide or a diffuser placed directly on the entrancewindow without interfering with the connections to the readoutelectronics.

[0040] Current silicon processing equipment for this technology usuallylimits the size of a detector wafer to approximately 10 cm to 20 cm indiameter. In order to make a detector with larger dimensions, ittypically is necessary to create modules on the wafers and cut them outfor further assembly. The individual modules can then be tiled togetherinto larger arrays. The basic structures according to the presentinvention may be built in form of modules with a minimum dead space atthe edges.

[0041] Detector arrays of the present invention may be coupled toCsI(Tl) scintillator arrays in various manners to achieve a seamlessboundary between modules. One method may include making smallerphotodetector pixels at the detector periphery to compensate for theexcess material outside of the active part of the device. Thescintillator pixels maintain a uniform size and pitch across boundariesof the photodetector modules. Another method may include sharing oflight from common scintillation pixels.

[0042] The detector array (e.g., at an entrance window) may be directlycoupled with the CsI(Tl) scintillator. The detector array may also becoupled with the CsI(Tl) scintillator via an interface that functions asa light guide between the entrance window and the CsI(Tl) scintillator.The interface may include a diffuser to spread the light coming out ofthe scintillator and may comprise glass, plastic, gel, grease and/or anyother suitable material. The interface may also be used to perform indexof refraction matching between the silicon detector (or silicon oxide orother entrance material on the detector) and the scintillator. It mayfurther be used to match non-flat surfaces of the scintillator and theentrance window.

[0043] The low cost and high yields of the structures in embodimentsaccording to the present invention coupled to CsI(Tl) scintillatingcrystals may allow for construction of large-sized solid state gammacameras and systems for Single Photon Emission Computed Tomography(SPECT) with superior performance and low cost.

[0044] Referring now to the drawings and in particular to FIG. 1, alight sensitive array 10 in an embodiment according to the presentinvention is constructed from n-type silicon (Si) 14. The n-type Si 14preferably is high resistivity Si, such resistivity preferably beingbetween 1000 ohm-cm to 20,000 ohm-cm. The light sensitive array 10 has acommon p⁺ light sensitive contact 20 on the front-side and ohmiccontacts implemented as a n⁺ pixelated array 24 on the back-side. The n⁺pixels on the back-side preferably are coupled to readout electronicsvia pre-amplifiers (not shown).

[0045] The p⁺ light sensitive contact preferably covers the entire lightsensitive array 10 and serves as a light sensitive window withsubstantially no dead areas. The p⁺ light sensitive contact 20 may alsobe referred to as an entrance window contact or as an entrance window.An electrically insulating layer 22, which may include SiO₂, surroundsthe entrance window on the front-side of the light sensitive array 10.

[0046] To isolate the individual n⁺ pixels 24, the inter-pixel gapcontains p⁺ separation implants 26 that surround each pixel in the formof a p⁺ grid 28 created on the entire array. In other embodiments, thep⁺ implants may form a number of p+ rings to isolate the individual n⁺pixels 24. The p+ grid or the p+ rings may be created on separate partsof the array, which may then be connected together externally, or theymay be placed directly on the entire silicon array.

[0047] A reverse bias preferably is applied between the n⁺ pixels 24 andthe p⁺ light sensitive contact 20 and between the n⁺ pixels 24 and thep⁺ grid 28. The value of an operational bias voltage −V_(B) 34 appliedto the p⁺ light sensitive contact 20 and the grid voltage −V_(G) 36applied to the p⁺ grid 28 may be different and should ensure pinch off30 between a front depleted region 32 extending from the front contacttoward the bulk of the substrate and a pixel depleted region 33extending from the pixels towards the bulk material. For example, V_(G)may range from −1 to −10 V (depending on substrate resistivity) andV_(B) may range from −10 to −200 V (depending on substrate resistivityand thickness). The pinch off 30 between these two depleted regions is acondition for proper pixel isolation. Before the pinch off occurs, thelight sensitive array 10 operates as a single photodiode.

[0048] The operational bias voltage, −V_(B) 34 applied to the p⁺ lightsensitive contact 20 may be lower by up to a factor of four than thebias voltage necessary to operate standard back-side illuminated siliconstructures fabricated from identical starting materials. During testingof the light sensitive array 10, it is not required to measure each ofthe (thousands of) individual pixels at a great expenditure of time andresources. Instead, a complete evaluation of the array may be achievedwith only two measurements. The first measurement is of the leakagecurrent of the fully biased p⁺ light sensitive contact 20 (withoutbiasing the p⁺ grid 28). The second measurement is of the leakagecurrent of the fully biased p⁺ grid 28 (without biasing the p⁺ lightsensitive contact 20). Measured values of the leakage currents less than10 nA/cm² for the p⁺ light sensitive contact 20 and p⁺ grid 28 may be anindication of the proper operation of the entire light sensitive array10. Leakage currents as low as 100 pA/cm² may be encountered duringthese measurements.

[0049]FIG. 2 is a block diagram of a light sensitive array 100 inanother embodiment according to the present invention. The lightsensitive array 110 is constructed from p-type Si 114. The p-type Si 114preferably is high resistivity Si. The light sensitive array 110 has acommon n⁺ light sensitive contact 120 on the front-side and ohmiccontacts implemented as a p⁺ pixelated array 124 on the back-side. TheP⁺ pixels on the back-side preferably are coupled to readout electronicsvia pre-amplifiers (not shown).

[0050] The n⁺ light sensitive contact 120 preferably covers the entirelight sensitive array 110 and serves as a light sensitive window withoutdead areas. The n⁺ light sensitive contact 120 may also be referred toas an entrance window contact or as an entrance window. An electricallyinsulating layer 122, which may include SiO₂, surrounds the entrancewindow on the front-side of the light sensitive array 10.

[0051] To isolate the individual p⁺ pixels 124, the interpixel gapcontains n⁺ separation implants 126 that surround each pixel in the formof an n⁺ grid 128 created on the entire array. In other embodiments, then⁺ implants may form a number of n⁺ rings to isolate the individual p⁺pixels 124. The n⁺ grid or the n⁺ rings may be created on separate partsof the array, which may then be connected together externally, or theymay be placed directly on the entire silicon array.

[0052] A reverse bias preferably is applied between the p⁺ pixels 124and the n⁺ light sensitive contact 120 and between the p⁺ pixels 124 andthe n⁺ grid 128. The value of an operational bias voltage +V_(B) 134applied to the n⁺ light sensitive contact 120 and the voltage +V_(G) 136applied to the n⁺ grid 128 may be different and should ensure pinch off130 between front and pixel depleted regions 132 and 133. The pinch off130 between these two depleted regions is a condition for proper pixelisolation. Before the pinch off occurs, the light sensitive array 110operates as a single photodiode.

[0053] The operational bias voltage, +V_(B) 134 applied to the n⁺ lightsensitive contact 120 may be lower by up to a factor of four than thebias voltage necessary to operate standard back-side illuminated siliconstructures fabricated from identical starting materials. During testingof the light sensitive array 110, it is not required to measure each ofthe (thousands of) individual pixels at a great expenditure of time andresources. Instead, a complete evaluation of the array may be achievedwith only two measurements. The first measurement is of the leakagecurrent of the fully biased n⁺ light sensitive contact 120 (withoutbiasing the n⁺ grid 128). The second measurement is of the leakagecurrent of the fully biased n⁺ grid 128 (without biasing the n⁺ lightsensitive contact 120). Measured values of the leakage currents lessthan 10 nA/cm² for the n⁺ light sensitive contact 120 and n⁺ grid 128may be an indication of the proper operation of the entire lightsensitive array 110. Leakage currents as low as 100 pA/cm² may beencountered during these measurements.

[0054]FIG. 3 is a block diagram of a light sensitive array (detectorarray) 12 according to one embodiment of the present invention. Thelight sensitive array 12 is constructed from n-type Si 14. The n-type Si14 preferably is high resistivity Si such resistivity preferably beingbetween 1000 ohm-cm to 20,000 ohm-cm. The light sensitive array 12 has acommon p⁺ junction electrode 20 on the front-side and ohmic contactsimplemented as an n⁺ pixelated array 24 on the back-side.

[0055] The light sensitive array 12 is similar to the light sensitivearray 10 of FIG. 1 in that the light sensitive array 12 preferably isbiased at the p⁺ junction electrode 20 and the p⁺ grid 28. In otherembodiments, the p⁺ grid 28 may not be biased. Instead, the frontdepletion region 32 may extend down to the p⁺ grid 28.

[0056] The p⁺ junction contact 20, which preferably covers the entirelight sensitive array 12, preferably is biased at a sufficiently highvoltage −V_(AV) 38 to achieve a controlled avalanche effect(amplification through electron impact ionization). The p⁺ junctioncontact 20 may also be referred to as an entrance window contact or asan entrance window.

[0057] To isolate the individual n⁺ pixels 24, the inter pixel gapcontains p⁺ separation implants 26 that surround each pixel in the formof p⁺ rings and/or a p⁺ grid 28 created on the entire array. In the caseof avalanche detector arrays, the electric field at the periphery 40 ofthe p+ junction contact 20 should be shaped in a particular manner so asto prevent premature surface breakdown.

[0058] This electric field shape may be achieved through animplementation of a beveled edge structure in the n-type Si 14. Thebevel may be formed by removing n-type Si material from the edge of thelight sensitive array 12 as represented by the broken lines 42, whichform a right triangle with the cross-sectional edge of the n-type Si 14.The hypotenuses of the right triangles formed on the left and rightsides of the n-type Si 14 indicate the slope of the bevel. The requiredshaping of the electric field at the periphery 40 may also be achievedthrough the use of guard rings and/or field plates.

[0059] In other embodiments, a p-type silicon may be used to implement alight sensitive array similar to the light sensitive array 12. In thelight sensitive array implemented using the p-type silicon, the entrancewindow would be implemented with n⁺ junction contact, the pixelatedarray would include p⁺ pixels, and a grid on the back-side would beimplemented using n⁺ implants.

[0060] The p+ grid implants 26 forming the grid pattern 28 in thepresent invention for a n-type substrate, and n+ grid implants 126forming the grid pattern 128 in the present invention for a p-typesubstrate may be designed in a variety of ways including, but notlimited to, possibility of separation of different sections of the gridwith independent biasing or floating of their sections.

[0061]FIG. 4 shows a construction of a grid pattern where highresistivity n-type Si 14 is used as the starting material. The readoutside of a device 50 in this case includes at least two grid patterns.One of the grid patterns 52 surrounds a second (interior) set of gridpatterns 54. In this case, it is possible to achieve one pixel size bybiasing the exterior sections of the grid 52 using voltage V₁, and tochange the size of the pixels by biasing the interior sections of thegrid 54 using voltage V₂. Using this method, the pixel size and theresulting spatial resolution of the detector array may be electronicallyregulated.

[0062] Referring now to FIG. 5, the individual interior gridarrangements 54 may be jointly biased by a single externally appliedvoltage using V₂ if the individual grids are coupled via a conductivebridge 60 placed over an electrical insulation layer 62 whichelectrically isolates the interior grid 54 from the exterior grid 52.This may be implemented as a part of planar silicon device fabricationusing standard photolithography tools, or after the wafers have beenprocessed on individual detectors using physical masks to define areasfor insulator and metal evaporations. Referring now to FIG. 6, theinterior grids such as 54 and 56 may be individually biased throughexternal connections to each such grid using voltages V₂ 54, V₃ 56, andthe like.

[0063] Although the present invention has been described in certainspecific embodiments, many additional modifications and variations wouldbe apparent to those skilled in the art. It is therefore to beunderstood that the present invention may be practiced otherwise than asspecifically described. Thus, the described embodiments of the presentinvention should be considered in all respects as illustrative and notrestrictive, the scope of the invention to be determined by the appendedclaims and their equivalents.

We claim:
 1. A detector array formed on a semiconductor material havinga first side and a second side, the detector array comprising: anentrance window formed on the first side, the entrance window being usedto receive radiation; and an array of detectors formed on the secondside, one or more of the detectors being used for detecting theradiation received via the entrance window, wherein the entrance windowforms a junction with the semiconductor material, and the detectorscomprise pixelated ohmic contacts.
 2. The detector array of claim 1,wherein one or more detectors are surrounded by one or more junctionseparation implants, the junction separation implants surrounding thedetectors in a form of a grid or rings.
 3. The detector array of claim1, wherein the entrance window is coupled to one selected from a groupconsisting of a scintillator, a scintillator array, a light guide or adiffuser for providing the radiation to the detector array via theentrance window.
 4. The detector array of claim 1, wherein one or moredetectors are coupled to readout electronics.
 5. The detector array ofclaim 2, wherein the semiconductor material is high resistivity n-typesilicon, the entrance window is p+ type, the array of detectors are n+type, and the junction separation implants are p+ type.
 6. The detectorarray of claim 2, wherein the semiconductor material is high resistivityp-type silicon, the entrance window is n+ type, the array of detectorsare p+ type and the junction separation implants are n+ type.
 7. Thedetector array of claim 1, wherein the array of detectors compriseradiation hardened detectors, and is used to detect at least oneradiation selected from a group consisting of particles, light, x-ray,and gamma-ray.
 8. The detector array of claim 1, wherein both theentrance window and the junction separation implants are reverse biased,and the reverse biasing generates in the semiconductor material a firstdepletion region originating at the first side and a plurality of seconddepletion regions originating at the second side with a pinch off regionformed between the first depletion region and at least one of the seconddepletion regions.
 9. The detector array of claim 1, wherein theentrance window is reverse biased with sufficiently high voltage so asto achieve a controlled avalanche effect.
 10. The detector array ofclaim 9, wherein electric field at a periphery of the junction betweenthe entrance window and the semiconductor material is shaped forpreventing premature surface breakdown.
 11. The detector array of claim10, wherein the electric field is shaped for preventing prematuresurface breakdown by removing material from the semiconductor materialat the edge of the detector array so as to produce a beveled edgestructure.
 12. The detector array of claim 10, wherein the electricfield is shaped for preventing premature breakdown by using guard ringsor field plates.
 13. The detector array of claim 1, wherein the gridsurrounding the detectors comprises an inner grid surrounding one ormore detectors and an outer grid surrounding the inner grid, wherein afirst pixel size is achieved by biasing the inner grid and a secondpixel size is achieved by biasing the outer grid, wherein the secondpixel size is larger than the first pixel size.
 14. The detector arrayof claim 1, wherein the entrance window is coupled with a CsI(Tl)scintillator.
 15. The detector array of claim 14, wherein the entrancewindow is directly coupled with the CsI(Tl) scintillator.
 16. Thedetector array of claim 14, wherein the entrance window is coupled withthe CsI(Tl) scintillator via an interface that functions as a lightguide between the entrance window and the CsI(Tl) scintillator.
 17. Thedetector array of claim 1, wherein the entrance window is coupled withone selected from a group consisting of CdWO₄, NaI(Tl), LSO and BGOscintillators.
 18. The detector array of claim 1, wherein the entrancewindow is directly coupled with one selected from the group consistingof CdWO₄, NaI(Tl), LSO and BGO scintillators.
 19. The detector array ofclaim 1, wherein the entrance window is coupled with one selected from agroup consisting of CdWO₄, NaI(Tl), LSO and BGO scintillators via aninterface that functions as a light guide between the entrance windowand the selected one of the scintillators.
 20. The detector array ofclaim 1, wherein the entrance window is optimized for receiving lightfrom a CsI(Tl) scintillator.
 21. The detector array of claim 1, whereinthe entrance window is optimized for receiving light from one selectedfrom a group consisting of light from CdWO₄, NaI(Tl), LSO, BGOscintillators.
 22. A method of forming a detector array on asemiconductor material having a first side and a second side, the methodcomprising the steps of: forming an entrance window on the first side,the entrance window is for receiving radiation; and forming an array ofdetectors on the second side, one or more of the detectors are used fordetecting the radiation received via the entrance window, wherein theentrance window forms a junction with the semiconductor material, andthe detectors comprise pixelated ohmic contacts.
 23. The method offorming a detector array of claim 22, the method further comprising thestep of: forming one or more junction separation implants, the junctionseparation implants surrounding the detectors in a form of a grid orrings.
 24. The method of forming a detector array of claim 22, themethod further comprising the step of: coupling the entrance window toone selected from a group consisting of a scintillator, a scintillatorarray, a light guide or a diffuser for providing the radiation to thedetector array via the entrance window.
 25. The method of forming adetector array of claim 22, the method further comprising the step of:coupling one or more detectors to readout electronics.
 26. The method offorming a detector array of claim 22, the method further comprising thesteps of: reverse biasing the entrance window; and reverse biasing thejunction separation implants, wherein the reverse biasing generates aplurality of depletion regions in the semiconductor material with apinch off region between at least one of the depletion regions locatedbetween the pinch off region and the first side and the rest of thedepletion regions located between the pinch off region and the secondside.
 27. The method of forming a detector array of claim 22, the methodfurther comprising the step of: reverse biasing the entrance window withsufficiently high voltage so as to achieve a controlled avalancheeffect.
 28. The method of forming a detector array of claim 25, themethod further comprising the step of: shaping electric field at aperiphery of the junction between the entrance window and thesemiconductor material to prevent premature surface breakdown.
 29. Themethod of forming a detector array of claim 28, wherein the shape of theelectric field is that of a beveled edge structure, wherein the bevelededge structure for the electric field is generated through removingmaterial from the semiconductor material at the edge of the detectorarray in a shape of the beveled edge structure.
 30. The method offorming a detector array of claim 28, wherein the shape of the electricfield is that of a beveled edge structure, wherein the beveled edgestructure for the electric field is generated using guard rings or fieldplates.
 31. The method of forming a detector array of claim 22, whereinthe grid surrounding the detectors comprises an inner grid surroundingone or more detectors and an outer grid surrounding the inner grid,wherein a first pixel size is achieved by biasing the inner grid and asecond pixel size is achieved by biasing the outer grid, wherein thesecond pixel size is larger than the first pixel size.
 32. A compositedetector array comprising a plurality of detector arrays, wherein atleast one of the detector arrays includes a detector array formed on asemiconductor material having a first side and a second side, thedetector array comprising: an entrance window formed on the first side,the entrance window being used to receive radiation; and an array ofdetectors formed on the second side, one or more of the detectors beingused to detect the radiation received via the entrance window, whereinthe entrance window forms a junction with the semiconductor material,and the detectors comprise pixelated ohmic contacts.
 33. A detectorarray formed on a semiconductor material having a first side and asecond side, the detector array comprising: entrance window means formedon the first side, the entrance window means being used for receivingradiation; and an array of detector means formed on the second side, oneor more of the detector means being used for detecting the radiationreceived via the entrance window means, wherein the entrance windowmeans form a junction with the semiconductor material, and the detectormeans comprise pixelated ohmic contacts.